This invention relates generally to the manufacture of semi-conductor devices. More particularly, the invention relates to a method of forming planarized wide filled trenches in the surface of a semi-conductor substrate, especially a silicon wafer, particularly filled with dielectric material, although the invention also can be used to form trenches filled with conductive material.
In the art of large-scale integrated chips, a large number of surface conductors are required for distribution of operating voltages and currents and digital signals between devices. Although surface conductors are insulated from the semi-conductor substrate upon which they are formed, a certain amount of capacitive coupling is present between the insulated conductor and the substrate through the insulating material. This capacitive coupling degrades the signal carried by the surface conductors.
While this capacitive coupling can be minimized by increasing the thickness of the dielectric material separating the conductors and the substrate, it is more desirable to recess the dielectric material below the surface of the substrate and maintain the planarity of the substrate rather than add the dielectric material onto the surface of the substrate. This is accomplished by forming shallow trenches in the surface of the substrate, and filling the trenches with dielectric material, normally silicon dioxide. These trenches may be either narrow trenches (i.e., less than about one micron in width, and more typically about 0.5 microns) and wide trenches (i.e., those wider than about one micron).
It is relatively simple to maintain planarity when forming dielectric filled narrow trenches. However, problems of maintaining planarity with the semi-conductor substrate and the dielectric material are presented with wide trenches because of the conformal nature of the deposition of the dielectric and especially silicon dioxide in the wide trenches.
There have been several prior art proposals for solving these problems of forming planarized dielectric filled wide trenches. One such proposal, described in U.S. Pat. No. 4,385,975 assigned to the assignee of this invention, utilizes a step in the process of depositing a photoresist material through a mask over the dielectric material contained in the trenches before planarization. The dielectric material is then reactive ion etched (RIE) with the photoresist masking the underlying material from etching, thus resulting in a relatively planer structure. U.S. Pat. No. 4,671,970 also utilizes a photoresist as a mask for reactive ion etching of dielectric material. These teachings of masking, while somewhat effective, nevertheless have certain drawbacks. They require extra masking and photolithographic steps, which adds two processing steps, and more importantly create significant problems of alignment; i.e., the mask must be perfectly aligned to deposit the photoresist exactly within the conformal or trough portion of the deposited dielectric material to be utilized to mask just that dielectric material desired and to expose the rest.
U.S. Pat. No. 4,278,987 shows a somewhat different technique for filling trenches, not with dielectric material, but with a semi-conductor material having a different characteristic than the base substrate material. This also uses a masking process.
U.S. application Ser. No. 189,863, filed May 3, 1988, owned by the assignee of this invention, discloses another technique for planarizing wide dielectric filled isolation trenches.
One of the principal objects of this invention is to provide an improved method of forming dielectric filled wide trenches in a semi-conductor substrate which is self-aligning and has resultant good planarization.